In recent years, the desirability of packaging several integrated circuit chips within a single package or compact module has been appreciated. The resulting package provides relatively complex electronic functions as well as improved performance, enhanced density and shortened interconnect lines.
Such packages generally comprise multi-chip carriers, which include a substrate for supporting the chips and on which is formed a high density interconnect grid, which provides interconnection between pads of the various chips and also provides a connection to leads at the periphery of the package.
The chips are bonded to the substrate. The electrical connections between the multi-chip carrier and the chip pads as well as between the carrier and the package-leads are established by using suitable existing technologies, such as wire bonding, tape automated bonding, laser interconnect deposition and flip-chip bump bonding. Passive elements such as capacitors and inductors may also be mounted on the substrate.
The manufacture of multi-chip carriers normally involves the deposition onto a substrate and patterning of four different metal layers, having four different insulation layers therebetween.
A typical manufacturing sequence is summarized hereinbelow:
A first metal layer, which may serve as a ground plane, is deposited on a substrate such as a glass plate, a ceramic plate or a silicon wafer.
A first insulation layer, such as polyimide or glass, is deposited over the first metal layer. Standard photolithography and etching techniques are employed to define vias through the insulation layer for connecting upper layers to the ground plane.
A second metal layer is deposited over the first insulation layer. This layer may serve as the power plane. Standard photolithography and etching techniques are employed to isolate the ground plane from the power plane by etching the metal around the previously formed vias.
A second insulation layer is deposited over the second metal layer. Standard photolithography and etching techniques are employed to define vias for connections of upper layers to the ground plane and power plane.
A third metal layer is deposited over the second insulation layer and patterned to form a bottom signal plane.
A third insulation layer is deposited over the third metal layer and patterned to define vias for connection to the underlying metal layers.
A fourth metal layer is deposited over the third insulation layer and patterned to form an upper signal plane which usually includes bonding pads by which the multi-chip carrier will be connected to the chips and to the package leads.
A fourth insulation layer is deposited over the fourth metal layer and patterned to define openings for the bonding pads.
The above-summarized process is long and costly and the product produced thereby is specific to a given application, such that each application requires a custom-made carrier.
An electrically programmable multi-chip carrier is described in an article entitled "Programmable Silicon Circuit Boards for High Density Packaging" in Semiconductor International, November 1987, page 32. This chip carrier is also described in an article entitled "An electrically programmable silicon circuit board," by Albert A. Bogdan, Proc. BUSCON'87 pp 156 ff.